1. Field of the Invention
The present invention relates to a semiconductor memory device (EEPROM) configured using electrically rewritable nonvolatile memory cells.
2. Description of the Related Art
Known as a nonvolatile semiconductor memory device that is electrically rewritable and enables a high level of integration (EEPROM) is a NAND flash memory. In a NAND flash memory, a NAND cell unit is configured by connecting in series a plurality of memory cells in a manner that neighboring cells share a source/drain diffusion layer. The two ends of the NAND cell unit are connected to a bit line and a source line, respectively, via select gate transistors. This kind of NAND cell unit configuration enables reduction in unit cell area and large capacity storage in comparison with a NOR type.
A memory cell of a NAND flash memory includes a charge accumulation layer (floating gate) formed on a semiconductor substrate with a tunnel insulator interposed, and a control gate stacked on the charge accumulation layer with an inter-gate insulator interposed, and stores data in a nonvolatile manner through a charge accumulation state of the floating gate. Specifically, two value data storage is effected by defining, for example, a high threshold voltage state where electrons are injected into the floating gate as data “0”, and defining a low threshold voltage state where electrons of the floating gate are discharged as data “1”. Recently, multi value storage of four values and so on is also undertaken by subdividing a threshold distribution for writing.
In addition, there is also developed a MONOS memory cell that uses as the charge accumulation layer a silicon nitride film in place of the floating gate. The MONOS memory cell has as the charge accumulation layer a silicon nitride film formed on the semiconductor substrate with a thin tunnel oxide film of about 2 nm interposed. Write and erase of data in the MONOS memory cell is effected by injecting electrons or holes into the silicon nitride film from the semiconductor substrate to change an amount of accumulated charge of the silicon nitride film, thereby altering a threshold voltage of the memory cell.
In a NAND flash memory, a plurality of NAND cell units are aligned in a word line direction; and an assembly of the NAND cell units that share word lines configures a block. Erase of data in the NAND flash memory is executed in units of such a block. In erase of data, a voltage of 0V is applied to word lines of a selected block while at the same time a voltage of a well where the memory cells are formed is boosted to an erase voltage. Data is erased by utilizing resultant potential difference between the word lines and the well to discharge electrons from the floating gates of the memory cells. Moreover, in the case of a MONOS memory cell, data is erased by injecting holes into the silicon nitride film that is a charge trap film.
At this time, a potential of word lines connected to a non-selected block where erasure of data is not to be executed is set to a floating state. That is to say, a gate of a transfer transistor configured to transfer a voltage of a control gate line to a word line in a row decoder is set to 0V, cutting off a connection between the word line and the control gate line in the non-selected block. The word lines of the non-selected block are thereby set to the floating state. The potential of the word lines in the floating state rises due to coupling with the well that is boosted to the erase voltage. Consequently, there is no occurrence of a large potential difference between the word lines and the well, and erase of data stored in the memory cells of the non-selected block can be prevented (refer to Japanese Unexamined Patent Application Publication No. 2000-21186).
Here, a problem arises with a leak current characteristic of the transfer transistors in the row decoder. It is preferable that the transfer transistors in the row decoder effect a complete cutoff; in other words, that after the word lines of the non-selected block that are in the floating state have their potential raised to a potential close to that of the well potential, charge does not flow off from the word lines. However, in reality, a leak current occurs in the transfer transistors, and, if an erase operation time becomes long, the potential of the word lines of the non-selected block falls due to this leak current. There is a problem that, in this case, the potential difference between the word lines and the well in the non-selected block increases, and data stored in the memory cells ends up being erased accidentally.
Particularly in the case of a MONOS memory cell, an erase characteristic of a memory cell deteriorates with increasing miniaturization. As a result, a prolonged erase operation (of, for example, 10 msec) becomes necessary. However, considering a possibility of accidental erasure of data stored in the memory cell, then the erase operation time cannot simply be extended, and it is necessary to increase a number of erase operation loops.